module ad_3pa1030(
  input                   sys_clk         ,
  input                   sys_rst_n       ,
  input       [9:0]       ad_data         ,
  input                   ad_otr          , 
  output                  ad_clk          

);

  PLL u_PLL
    (
    // Clock out ports
    .clk_out1(ad_clk),     // output clk_out1
    // Status and control signals
    .locked(locked),       // output locked
    // Clock in ports
    .clk_in1(sys_clk)
    );   
endmodule